High data rate spread-spectrum system and method

ABSTRACT

A high data rate, high processing gain, direct sequence spread spectrum system that transmits a BPSK or QPSK signal. The system FEC encodes and interleaves data which are collected and stored and forwarded N bits at a time by transmitting one of 2 N  pseudo random waveforms every time N bits are collected. The 2 N  pseudo random waveforms can be sent as an orthogonal, bi-orthogonal, or nearly orthogonal waveform. During acquisition, a plurality of product devices multiply a received spread-spectrum signal by a header chip-sequence signal. In each case, the header chip-sequence signal has a different delay, with each delay being at most one chip. Acquisition can also be achieved using a matched filter. After acquisition, the plurality of product device multiply the received spread-spectrum signal by 2 N  chip-sequence signals to generate a plurality of products, with each chip-sequence signal of the plurality of chip-sequences signals being different from other chip-sequence signals of the plurality of chip-sequence signals; a plurality of integrators integrate the plurality of products thereby forming 2 N  correlators, and a comparator selects a largest value from the plurality of integrators. The largest value is decoded into N bits of data. This process is repeated for each N bit word received.

RELATED PATENTS

[0001] This patent stems from a continuation application of U.S. patentapplication Ser. No. 09/186,246, and filing date of Nov. 4, 1998,entitled HIGH DATA RATE SPREAD-SPECTRUM SYSTEM AND METHOD by inventor,DONALD L. SCHILLING, which stems from a continuation application of U.S.patent application Ser. No. 09/186,246, and filing date of Nov. 4, 1998,entitled HIGH DATA RATE SPREAD-SPECTRUM SYSTEM AND METHOD by inventor,DONALD L. SCHILLING. The benefit of the earlier filing date of theparent patent application is claimed for common subject matter pursuantto 35 U.S.C. § 120.

BACKGROUND OF THE INVENTION

[0002] This invention relates to communications, and more particularlyto a high data rate spread-spectrum system.

DESCRIPTION OF THE RELEVANT ART

[0003] In a fixed bandwidth CDMA system, increasing the data ratereduces the processing gain. To maintain a high data rate, the prior artteaches the transmission of spread-spectrum signals with parallelorthogonal chip-sequence signals. The use of parallel chip-sequencesignals, however, results in increased interference in the receiver dueto multipath. In addition, when transmitting parallel chip-sequencesignals, the transmitted output signal usually is distorted as a resultof nonlinearities in the output amplifiers and filters.

[0004]FIGS. 1 and 2 show a prior art spread-spectrum system,transmitting data at high processing gain. The example is for an encodeddata rate of 100 megabits per second (Mb/s), although any data ratecould be used. The data are demultiplexed by demultiplexer 45 into fourdata streams, each with a symbol rate of 25 mega-symbols/second. Fourproduct devices 41, 42, 443, multiply the four data streams by fourorthogonal chip-sequence signals g₁(t), . . . , g₄(t), fromchip-sequence generator 44, which have a chip rate of 400mega-chips/second. The four chip-sequence signals could be sent asfive-level pulse amplitude modulation (PAM), by multiplying by cos ω₀tor as three amplitudes in each of cos ω_(o)t and sin ω₀t axes. Theoutputs from the product devices 41, 42, 443 are combined by combiner46, and transmitted as a radio wave, at a carrier frequency ω_(o), overa communications channel. Signal source 16 and product device 15translate the output from combiner 46 to the carrier frequency, using astandard up-converter device. The antenna 17 is coupled to the radiowave to the communications channel.

[0005] The receiver has four matched filters 711, 712, 714 for detectingthe four parallel signals. At the receiver, antenna 24, product device25 and receiver signal source 26 receive and translate the multichannelspread-spectrum signal to a processing frequency. The multiplexer 54multiplexes the outputs from the matched filters 711, 712, 714.De-interleaver 37 de-interleaves the multiplexed data, and FEC decoder38 decodes the de-interleaved data as estimated data.

[0006] Multipath causes delayed versions of g₁(t), g₂(t), g₃(t) andg₄(t) to be present at each matched filter. Consider the first matchedfilter 711. The delayed versions are not orthogonal to the firstchip-sequence signal g₁(t) and multipath interference results. Thenumber of interferers is due to the number of parallel codes, number ofsimultaneous users, etc.

[0007] Further, any multipath signals can be generated by each of themultilevel pulse amplitude modulation signals, which can produce one ofM levels for each chip. The number of levels produced is M. This largevariation in amplitude results in distortion due to filtering and tononlinearities in the transmit output amplifier.

SUMMARY OF THE INVENTION

[0008] A general object of the invention is to facilitate thetransmission and reception of a high data rate signal using a highprocessing gain CDMA system without using parallel codes.

[0009] A second object is the efficient acquisition and synchronizationof such a signal.

[0010] According to the present invention, as embodied and broadlydescribed herein, an improvement to a spread-spectrum system is providedfor sending data over a communications channel. The spread-spectrumsystem is assumed to handle high data rate communications. Theimprovement includes, at the transmitter, a memory which typically iscoupled to a bit interleaver, and a chip-sequence encoder, which iscoupled to the memory and to a transmitter section. At the receiver, theimprovement includes a plurality of product devices, a plurality ofintegrators, a comparator, and a chip-sequence-signal generator andcontroller.

[0011] At the transmitter, the memory stores N bits of interleaved data,or other data, from an interleaver, or other data source, respectively.The chip-sequence encoder uses the N bits of stored data for selectingone of 2^(N) orthogonal chip-sequence signals stored in thechip-sequence encoder. The chip-sequence encoder outputs the selectedchip-sequence signal. The number of bits, N, is the number of bits in asymbol, used for selecting one of the 2^(N) chip-sequence signals. Whileorthogonal signals are preferred, near-orthogonal signals also can beemployed, albeit at the cost of a slightly higher error rate.

[0012] At the receiver, at the processing frequency, 2^(N) correlatorsare employed, one for each of the 2^(N) possible signals. The outputsfrom the 2^(N) correlators are compared, and the output with the largestvalue is chosen. 2^(N) matched filters also could be employed, however,using matched filters is not a preferred approach since 2^(N) matchedfilters would require more gates, and therefore more cost.

[0013] For acquisition, the 2^(N) product devices multiplies thereceived header of the spread-spectrum signal by a replica of the headersignal, which is stored or generated at the receiver, and whichtypically is taken from the plurality of 2^(N) chip-sequence signals.Each correlator is delayed, one from the other, by one-half chip in apreferred system. The chip-sequence signal has the first chip-sequencesignal, and has a delay of at least one chip with respect to eachchip-sequence signal from the plurality of 2^(N) chip-sequence signals.Each chip-sequence signal has a different delay from other chip-sequencesignals from the plurality of 2^(N) chip-sequence signals. Timing isobtained by using the timing of the correlator with the largest output.

[0014] The plurality of product devices, after acquisition, multipliesthe received spread-spectrum signal by the plurality of 2^(N)chip-sequence signals, with each chip-sequence signal from the pluralityof 2^(N) chip-sequence signals having a different chip-sequence signalfrom other chip-sequence signals from the plurality of 2^(N)chip-sequence signals. The plurality of integrators are coupled to theplurality of product devices, respectively. The plurality of integratorsintegrate a plurality of products from the plurality of product devicesduring the period of a chip-sequence signal. The comparator, which iscoupled to the plurality of integrators, selects a largest value fromthe plurality of integrators. The chip-sequence decoder decodes thelargest value from a respective integrator of the plurality ofintegrators into N bits of data or interleaved data, depending on theoriginating source at the transmitter.

[0015] Additional objects and advantages of the invention are set forthin part in the description which follows, and in part are obvious fromthe description, or may be learned by practice of the invention. Theobjects and advantages of the invention also may be realized andattained by means of the instrumentalities and combinations particularlypointed out in the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings, which are incorporated in andconstitute a part of the specification, illustrate preferred embodimentsof the invention, and together with the description serve to explain theprinciples of the invention.

[0017]FIG. 1 illustrates a prior art approach for transmitting data at ahigh rate in a CDMA system;

[0018]FIG. 2 illustrates a prior art approach for receiving data at ahigh rate in a CDMA system;

[0019]FIG. 3 is a block diagram of a transmitter for increasingprocessing gain in a high data rate system for orthogonal BPSK;

[0020]FIG. 4 is a block diagram of a transmitter for increasingprocessing gain in a high data rate system for bi-orthogonal BPSK;

[0021]FIG. 5 is a block diagram of a transmitter for increasingprocessing gain in a high data rate system for orthogonal QPSK;

[0022]FIG. 6 is a block diagram of a transmitter for increasingprocessing gain in a high data rate system for bi-orthogonal QPSK;

[0023]FIG. 7 is a block diagram of a receiver for increasing processinggain in a high data rate system for BPSK; and

[0024]FIG. 8 is a block diagram of a receiver for increasing processinggain in a high data rate system for QPSK.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0025] Reference now is made in detail to the present preferredembodiments of the invention, examples of which are illustrated in theaccompanying drawings, wherein like reference numerals indicate likeelements throughout the several views.

[0026] The invention disclosed in this patent is a novel approach toincreasing data rate over a spread-spectrum system. The claimedinvention may be manufactured, in whole or in part, as a digital signalprocessor (DSP), as an application specific integrated circuit (ASIC),from a general purpose processor, from discrete and/or analog electroniccomponents, or as a combination of one or more of the DSP, ASIC, generalpurpose processor and discrete and/or analog components.

[0027] The present invention broadly includes FEC means, interleavermeans, memory means, chip-encoder means, transmitter means, receivermeans, spread-spectrum means, comparator means, chip-decoder means,deinterleaver means, and FEC-decoder means. The interleaver means iscoupled between the FEC-encoder means and the memory means. Thechip-encoder means is coupled between the memory means and thetransmitter means. The transmitter means is coupled to thecommunications channel.

[0028] The receiver means is coupled to the communications channel. Thespread-spectrum means is coupled between the receiver means and thecomparator means. The chip-decoder means is coupled between thecomparator means and the deinterleaver means.

[0029] The FEC-decoder means is coupled to the deinterleaver means. TheFEC-encoder means encodes with an FEC code, the data as FEC data. FECdata, as used herein, are the encoded data from any data source whichare at the output of the FEC-encoder means.

[0030] The interleaver means interleaves the FEC data as interleaveddata. The memory means stores N bits of interleaved data as stored data.As used herein, stored data are the data stored in the memory means. Nis the number of bits in a particular symbol.

[0031] The chip-encoder means selects a chip-sequence signal, based onthe N bits of stored data, from one of 2^(N) chip-sequence signalsstored in the chip-encoder means. The selected chip-sequence signal isan output chip-sequence signal. In a preferred system, the 2′chip-sequence signals are orthogonal and each chip-sequence signal has2^(N) chips. Alternatively, 2^(N)/2 orthogonal chip-sequence signals canbe selected and each chip-sequence signal can be sent as a positive ornegative signal, creating bi-orthogonal signaling.

[0032] The transmitter means translates the output chip-sequence signalto a carrier frequency and transmits the output chip-sequence signal atthe carrier frequency as a radio wave over a communications channel, asa binary phase-shift-keyed (BPSK) or as a quaternary phase-shift-keyed(QPSK) spread-spectrum signal.

[0033] The receiver means translates the spread-spectrum signal receivedto a processing frequency. Because of the ease of digital processing, apreferred procedure is to translate, or down convert, the receivedspread-spectrum signal to baseband.

[0034] The spread-spectrum means, for acquisition, multiplies thereceived spread-spectrum signal by a plurality of “header” chip-sequencesignals. Each header chip-sequence signal has an identical chipsequence. Each header chip-sequence signal has a different delay fromthe other header chip-sequence signals. The preferred delay is one-halfchip duration, although one chip duration is also workable. Thisaccomplishes acquisition, by multiplying the received spread-spectrumsignal by an identical chip-sequence signal, with different delays. Theoutput of each multiplier is added forming a correlation, and thecorrelator with the largest output is selected. This approach permitsthe same 2^(N) correlators used for demodulation to be used foracquisition by changing the multiplying signals. A matched filter,however, could be used for acquisition, but using a matched filter wouldincrease hardware. Using a matched filter as a separate circuit foracquisition, which would be in addition to the embodiment disclosedherein, is well know in the art.

[0035] After acquisition, the spread-spectrum means changes frommultiplying by an identical “header” chip-sequence signal to multiplyingby the 2^(N) different chip-sequence signals of the plurality of 2^(N)chip-sequence signals. Accordingly, after acquisition, the receivedspread-spectrum signal is multiplied by each of the chip-sequencesignals in the plurality of chip-sequence signals, with eachchip-sequence signal in the plurality of chip-sequence signals having adifferent chip sequence from other chip-sequence signals from theplurality of chip-sequence signals. The outputs of each multiplier isadded so that each multiplier-adder is a correlator.

[0036] The comparator means selects the largest value at the output ofthe spread-spectrum means at each symbol time T_(s).

[0037] The decoder means 36 decodes the largest value from thecomparator means as an N-bit sequence or series of N-bits.

[0038] The deinterleaver means deinterleaves the series of bits fromchip-decoder means to deinterleaved data, and the FEC-decoder meansdecodes the deinterleaved data as estimated data.

[0039] The data, d(t), are FEC encoded and interleaved, and successive Nbits are stored. Each N bit sequence is considered a symbol. For each Nbits, one of 2^(N) orthogonal sequences is selected. Each sequence has2^(N) chips/symbol. Each sequence is then amplitude modulation (AM)modulated. Thus the following signal is sent:

k _(i)(t)cos ω_(o) t i=1, 2, . . . , 2^(N)

or $\begin{matrix}{{{{k_{i}(t)}\cos \quad \omega_{o}t\quad i} = 1},2,\ldots \quad,2^{N}} \\{or} \\{{{{{k_{i}(t)}\cos \quad \omega_{o}t} + {{h_{j}(t)}\sin \quad \omega_{o}t\quad i}} = 1},2,\ldots \quad,\frac{2^{N}}{2}} \\{\quad {{j = 1},2,\ldots \quad,\frac{2^{N}}{2}}}\end{matrix}$

[0040] Alternatively, bi-orthogonal signaling may be used by$\begin{matrix}{{{{p_{i}(t)}\cos \quad \omega_{o}t\quad i} = 1},2,\ldots \quad,\frac{2^{N}}{2}} \\{or} \\{{{{{\pm {g_{i}(t)}}\cos \quad \omega_{o}t} \pm {{h_{j}(t)}\cos \quad \omega_{o}t\quad i}} = 1},2,\ldots \quad,\frac{2^{N}}{4}} \\{\quad {{j = 1},2,\ldots \quad,\frac{2^{N}}{4}}}\end{matrix}$

[0041] where each waveform is orthogonal or bi-orthogonal to the others.In the receiver, 2^(N) correlators are used. If bi-orthogonal codingwere used, then 2^(N−1) correlators are required.

[0042] The relevant formulas are:

Processing Gain (PG)=2^(N) chips/symbol

f _(s) =f _(b) /N $f_{c} = {{2^{N}f_{s}} = {\frac{2^{N}}{N}f_{b}}}$

[0043] Where f_(b) is frequency (bandwidth) of bits, f_(c) is frequency(bandwidth) of chips, and f₁ is frequency (bandwidth) of symbols.

[0044] The number of correlators, or matched filters, needed are:

[0045] 2^(N) /N for orthogonal coding

[0046] 2^(N)/2N for bi-orthogonal coding

[0047] For example:

f _(b)=100 Mb/s

[0048] and PG=16

[0049] Then 16=2^(N) and N=4

f _(s) =f _(b) /N=25 MHz

[0050] and f_(s)=400 MHz

[0051] N=4 for orthogonal coding

[0052] N=2 for bi-orthogonal coding

[0053] In the exemplary arrangement shown in FIGS. 3-6, the improvementto the transmitter includes, by way of example, aforward-error-correction (FEC) encoder 11, interleaver 12, and memory13. In FIGS. 3 and 4, a chip-sequence encoder 14 is employed forselecting one of 2^(N) chip-sequence signals. The transmitter section,in FIGS. 3 and 4, includes a product device 15, a signal source 16, andan antenna 17. Additional amplifiers and filters may be employed in thetransmitter section, as is well known in the art. The interleaver 12 iscoupled between the FEC encoder 11 and the memory 13. The chip-sequenceencoder 14 is coupled between the memory 13 and the product device 15.The signal source 16 is coupled to the product device 15, and theantenna 17 is coupled to the product device 15.

[0054] The FEC encoder 11, of FIGS. 3-6, encodes the data with an FECcode. A convolutional encoder, concatenated coder comprising aconvolutional and a Reed Solomon (RS) encoder, or other error-correctingcodes can be used. The output of the FEC encoder 11 is denoted herein asFEC data.

[0055] The interleaver 12 interleaves the FEC data, using a bitinterleaver algorithm as is well known in the art. The output of theinterleaver 12 is denoted herein as interleaved data.

[0056] The memory 13 stores N bits of data. The data may come from theinterleaver 12, and from other sources, such as signaling and otheroverhead data into the memory 13. The data stored in the memory 13 isdenoted herein as stored data. The number N represents the number ofbits per symbol. The symbols are used or represented for a particularchip-sequence at the chip-sequence encoder 14.

[0057] Referring to FIGS. 3 and 4, the chip-sequence encoder 14 uses Nbits of stored data for selecting a particular chip-sequence signal froma plurality of chip-sequence signals. The plurality of chip-sequencesignals, in a preferred embodiment, includes 2^(N) orthogonalchip-sequence signals. The 2^(N) chip-sequence signals are stored in thechip-sequence encoder 14. In response to the N bits of data stored eachsymbol time T_(s), one of the 2^(N) signals is outputted from thechip-sequence encoder 14. The output of the chip-sequence encoder 14 isdenoted herein as an output chip-sequence signal. In FIG. 4, the outputof the chip-sequence encoder 14 is multiplied by gate 115 with a plus orminus one, to generate a bi-orthogonal BPSK signal.

[0058] Referring to FIGS. 5 and 6, the chip-sequence encoders 214, 314uses 2^(N)/2 bits of stored data for selecting a particularchip-sequence signal from a plurality of chip-sequence signals. Theplurality of chip-sequence signals, in a preferred embodiment, includes2^(N)/2 bi-orthogonal chip-sequence signals. The 2^(N)/2 chip-sequencesignals are stored in the chip-sequence encoders 214, 314. In responseto the N bits of data stored each symbol time T_(s), one of the 2^(N)/2signals is outputted from the chip-sequence encoders 214, 314. Theoutput of the chip-sequence encoder 214 is denoted herein as aquadrature-phase output chip-sequence signal, and the output from thechip-sequence encoder 314 is denoted herein as an inphase chip-sequencesignal. The signal source 16 generates an in-phase carrier signal, andphase shifter 416 generates the quadrature-phase carrier signal, as iswell known in the art.

[0059] In FIG. 6, the outputs of the chip-sequence encoders 214, 314 aremultiplied by multiplier devices 216, 316, respectively, by thequadrature-phase carrier signal and the in-phase carrier signal, and bygates 217, 317, respectively, with a plus or minus one, to generate abi-orthogonal QPSK signal.

[0060] The transmitter section translates the output chip-sequencesignal to a carrier frequency, and transmits, as a radio wave, theoutput chip-sequence signal at the carrier frequency over acommunications channel. The transmitted signal is a spread-spectrumsignal.

[0061] At the transmitter section in FIGS. 3 and 4, the signal source 16generates the signal for translating the output chip-sequence signal tothe particular carrier frequency, and the product device 15 multipliesthe output chip-sequence signal to the carrier frequency. The resultingproduct is the spread-spectrum signal which is radiated by the antenna17. For FIGS. 3 and 4 the product device 15 and signal source 16 areshown for an in-phase carrier.

[0062] At the transmitter section in FIGS. 5 and 6, the signal source 16generates the signal for translating the output chip-sequence signal tothe particular carrier frequency, and the product devices 216, 316multiplies the output chip-sequence signal to the carrier frequency. Thephase-shift device 416 generates the quadrature component from thesignal source 16. The resulting product is the spread-spectrum signalwhich is radiated by the antenna 17. Note that in FIGS. 5 and 6, a setof quadrature carriers, cos ω_(o)t and sin ω_(o)t, are generated inplace of a simple in-phase carrier, of FIGS. 3 and 4.

[0063]FIG. 7 shows how the basic receiver circuit, shown in FIG. 2, ismodified by the addition of a sequence detector that detects a symbolheader. This decoder could be a simple matched filter which operates onthe symbols.

[0064] At the receiver, the receiver section translates thespread-spectrum signal to a processing frequency. The receiver sectionhas an antenna 24 which is coupled to the communications channel, and asignal source 26. The signal source 26 generates a signal whichtranslates the received spread-spectrum signal by the mixer or productdevice 25, to the processing frequency. In practice, as shown in FIG. 8,two quadrature terms are obtained by multiplying by cos ω_(o)t and sinω_(o)t and using standard receiver circuits. FIG. 8 illustrates anin-phase device 25 and a quadrature-phase device 225, coupled to asignal source 26 for cos ω_(o)t and a signal source 226 for sin ω_(o)t.Alternatively, a single signal source and a phase shifter could be useto generate the cos ω_(o)t and sin ω_(o)t signals.

[0065] In FIG. 7, the plurality of product devices 21, 22, 23 arecoupled to the product device 25. The plurality of product devices 21,22, 23 operates in cooperation with the chip-sequence-signal generatorand controller 27. For acquisition, a “header” chip-sequence signal isgenerated by the chip-sequence-signal generator and controller 27. Theheader chip-sequence signal is generated as a plurality of headerchip-sequence signals, with each chip-sequence signal in the pluralityof header chip-sequence signals having a delay of one-half chip or onechip delay with respect to each other chip-sequence signal in theplurality of header chip-sequence signals. Thus, each of the headerchip-sequence signals in the plurality of header chip-sequence signalshas an identical chip sequence as the first chip-sequence signal, butwith a different delay. The plurality of product devices 21, 22, 23multiplies the received spread-spectrum signal by the plurality ofheader chip-sequence signals, each with a respective, different delay.At the output of the plurality of product devices 21, 22, 23, theplurality of integrators 31, 32, 33 integrates, respectively, aplurality of products from the plurality of product devices 21, 22, 23.The products are integrated for a period of a header-chip-sequencesignal.

[0066] The quadrature detection embodiment of FIG. 8 operatesfunctionally equivalent to the in-phase embodiment described for FIG. 7,with the addition of quadrature-phase products devices 221, 222, 223 andquadrature-phase integrators 231, 232, 233. A set of a product device 21and an integrator 31, comprise a correlator, as is well known in theart.

[0067] The comparator 35 selects a largest value from the plurality ofintegrators 31, 32, 33, and for the quadrature-phase embodiment, of FIG.8, also from the plurality of integrators 31, 32, 33, 231, 232, 233.When the largest value is selected by the comparator 35, a controlsignal is sent to the chip-sequence signal-generator and controller 27,as to which of the particular paths from the plurality of productdevices 21, 22, 23 and the respective plurality of integrators 31, 32,33 has the largest value. The chip-sequence-signal generator andcontroller 27 locks onto the timing of the selected signal path.

[0068] Alternatively, a separate matched filter receiver could be usedto detect the header and achieve synchronization.

[0069] When the chip-sequence-signal generator and controller 27 arelocked into the timing, the chip-sequence-signal generator andcontroller 27 generates a plurality of chip-sequence signals, with eachchip-sequence signal different from the other chip-sequence signals inthe plurality of chip-sequence signals and each being one of the 2^(N),or 2^(N)/2, possible transmitted signals. Thus, each chip-sequencesignal from the chip-sequence-signal generator and controller 27 isdifferent from the other chip-sequence signals in the plurality ofchip-sequence signals, by having a different chip sequence from otherchip-sequence signals. The plurality of chip-sequence signals are fed tothe plurality of product devices 21, 22, 23, in time synchronizationwith the received spread-spectrum signal, since acquisition has beenachieved.

[0070] Acquisition is achieved by transmitting a prescribed number ofchips to form the header. For example, if the desired signal-to-noiseratio (SNR) at the correlator output for a single sequence were 20 dB,and the SNR of a chip were −10 dB, then a sequence of 1000 chips isadequate. In this case, assuming a chip rate of 4 Megachips/second, theacquisition time T_(A)=(1000/4) microseconds=250 microseconds.

[0071] After acquisition, the plurality of product devices 21, 22, 23,the chip-sequence-signal generator and controller 27, and plurality ofintegrators 31, 32, 33 serve to demodulate which chip-sequence signal isembedded in the received spread-spectrum signal. The strongest signalpath from the plurality of integrators 31, 32, 33 is selected bycomparator 35 as the detected signal. Upon detecting a particularchip-sequence signal from a particular path, the selected chip-sequencesignal is decoded to N bits by chip decoder 36. The de-interleaver 37deinterleaves the interleaved N bits and the FEC decoder decodes thedeinterleaved data. An estimate of data is output from the FEC decoder38.

[0072] To ensure timing accuracy, the system could sample two or moretimes per chip. For data rates between 64 kb/s and 2 Mb/s, technologypermits sampling at four times the chip rate. However, at data rates of100 Mb/s and a chip rate of 400 Mchips/s, one or two samples per chipappears to be the technological limit today.

[0073]FIG. 8 shows that quadrature detection is actually employed.

[0074] The present invention also includes a spread-spectrum methodimprovement for sending data over a communications channel, comprisingthe steps of storing, at a transmitter, N bits of interleaved data asstored data, with N a number of bits in a symbol, and selecting, at thetransmitter in response to the N bits of stored data, a chip-sequencesignal from a plurality of chip-sequence signals, as an outputchip-sequence signal. The method then comprises the steps oftransmitting the output chip-sequence signal as a radio wave, at acarrier frequency, over the communications channel, as a spread-spectrumsignal and, translating, at a receiver, the spread-spectrum signal to aprocessing frequency as a received spread-spectrum signal. Foracquisition, the received spread-spectrum signal is multiplied, at theprocessing frequency, by a header chip-sequence signal from theplurality of chip-sequence signals, with each chip-sequence signalhaving an identical chip sequence as the header chip-sequence signal,but with each chip-sequence signal having a delay of one-half or onechip, with each chip-sequence signal from the plurality of chip-sequencesignals having a different delay from other chip-sequence signals. Afteracquisition, the received spread-spectrum signal is multiplied by theplurality of chip-sequence signals, with each chip-sequence signal fromthe plurality of 2^(N) chip-sequence signals having a different chipsequence from other chip-sequence signals in the plurality ofchip-sequence signals, respectively. A plurality of products from theplurality of product devices are integrated during a period of achip-sequence signal, and a largest value is selected from the pluralityof integrators. The largest value from a respective integrator of theplurality of integrators is decoded into N bits of interleaved data.

[0075] The invention preferably uses orthogonal or bi-orthogonalsignaling to increase the processing gain. The result is a binary AMsignal (BPSK) or a QPSK signal and, therefore, the waveform is notdegraded by amplifier nonlinearities. Further, since only one waveformis sent and RAKE is employed in the receiver, multipath can be used toenhance performance.

[0076] It will be apparent to those skilled in the art that variousmodifications can be made to the technique to acquire synchronization inhigh data rate CDMA systems of the instant invention without departingfrom the scope or spirit of the invention, and it is intended that thepresent invention cover modifications and variations of the technique toacquire synchronization in high data rate CDMA systems provided theycome within the scope of the appended claims and their equivalents.

I claim:
 1. A spread-spectrum system for sending data over acommunications channel, comprising: a forward-error-correction (FEC)encoder for encoding, with an FEC code, the data as FEC data; aninterleaver, coupled to said FEC encoder, for interleaving the FEC dataas interleaved data; a memory, coupled to said interleaver, for storingN bits of interleaved data as stored data, with N a number of bits in asymbol; a chip-sequence encoder, coupled to said memory, for selecting,responsive to the N bits of stored data, a chip-sequence signal from2^(N) chip-sequence signals stored in said chip-sequence encoder, as anoutput chip-sequence signal of said chip-sequence encoder; a transmittersection, coupled to said chip-sequence encoder, for transmitting theoutput chip-sequence signal as a radio wave, at a carrier frequency,over said communications channel, as a spread-spectrum signal; areceiver section, coupled to said communications channel, fortranslating the spread-spectrum signal to a processing frequency as areceived spread-spectrum signal; a plurality of product devices, coupledto said receiver section, for multiplying, at the processing frequency,for acquisition, the received spread-spectrum signal by a headerchip-sequence signal with each chip-sequence signal having an identicalchip sequence as the header chip-sequence signal, each chip-sequencesignal having a delay of one-half or one chip relative to one anotherand having a different delay from other chip-sequence signals; saidplurality of product devices for multiplying, after acquisition, thereceived spread-spectrum signal by the plurality of 2^(N) chip-sequencesignals, with each chip-sequence signal from the plurality of 2^(N)chip-sequence signals having a different chip sequence from otherchip-sequence signals in the plurality of 2^(N) chip-sequence signals,respectively; a plurality of integrators coupled to said plurality ofproduct devices, respectively, for integrating a plurality of productsfrom the plurality of product devices during a period of a chip-sequencesignal thereby forming 2^(N) correlators; a comparator, coupled to saidplurality of integrators, for selecting a largest value from theplurality of integrators; a chip-sequence decoder, coupled to saidcomparator, for decoding the largest value from a respective integratorof said plurality of integrators, into N bits of interleaved data; adeinterleaver, coupled to said chip-sequence decoder, for deinterleavinga series of interleaved bits from said chip-sequence decoder, asdeinterleaved data; and a FEC decoder, coupled to said deinterleaver,for FEC decoding the deinterleaved data as estimated data.
 2. Animprovement to a spread-spectrum system for sending data over acommunications channel, comprising: memory means for storing N bits ofdata as stored data, with N a number of bits in a symbol; chip-encodermeans, coupled to said memory means, for selecting, responsive to the Nbits of stored data, a chip-sequence signal from a plurality of 2^(N)chip-sequence signals stored in said chip-sequence encoder, as an outputchip-sequence signal of said chip-encoder means; a transmitter section,coupled to said chip-encoder means, for transmitting the outputchip-sequence signal as a radio wave, at a carrier frequency, over saidcommunications channel, as a spread-spectrum signal; a receiver section,coupled to said communications channel, for translating thespread-spectrum signal to a processing frequency as a receivedspread-spectrum signal; spread-spectrum means, coupled to said receiversection, for processing, at the processing frequency, for acquisition,the received spread-spectrum signal by a header chip-sequence signalfrom the plurality of chip-sequence signals, with each chip-sequencesignal of the plurality of chip-sequence signals set for having anidentical chip sequence as the header chip-sequence signal, eachchip-sequence signal having a delay of one-half or one chip, with eachchip-sequence signal from the plurality of chip-sequence signals havinga different delay from other chip-sequence signals, said spread-spectrummeans for processing, after acquisition, the received spread-spectrumsignal by the plurality of chip-sequence signals with each chip-sequencesignal from the plurality of chip-sequence signals having a differentchip sequence from other chip-sequence signals in the plurality ofchip-sequence signals, respectively; integrator means coupled to saidspread-spectrum means, for integrating a plurality of output signalsfrom said spread-spectrum means during a period of a chip-sequencesignal; comparator means, coupled to said integrator means, forselecting a largest value from said integrator means; and chip-decodermeans, coupled to said comparator means, for decoding the largest valuefrom said integrator means into N bits of estimated data.
 3. Animprovement to a spread-spectrum system for sending data over acommunications channel, comprising: a memory for storing N bits of dataas stored data, with N a number of bits in a symbol; a chip-sequenceencoder, coupled to said memory, for selecting, responsive to the N bitsof stored data, a chip-sequence signal from a plurality of chip-sequencesignals stored in said chip-sequence encoder, as an output chip-sequencesignal; a transmitter section, coupled to said chip-sequence encoder,for transmitting the output chip-sequence signal as a radio wave, at acarrier frequency, over said communications channel, as aspread-spectrum signal; a receiver section, coupled to saidcommunications channel, for translating the spread-spectrum signal to aprocessing frequency as a received spread-spectrum signal; a pluralityof product devices, coupled to said receiver section, for multiplying,at the processing frequency, for acquisition, the receivedspread-spectrum signal by a header chip-sequence signal from theplurality of chip-sequence signals, with each chip-sequence signal ofthe plurality of chip-sequence signals set having an identical chipsequence as the header chip-sequence signal, each chip-sequence signalhaving a delay of at most one chip, with each chip-sequence signal fromthe plurality of chip-sequence signals having a different delay fromother chip-sequence signals, said plurality of product devices formultiplying, after acquisition, the received spread-spectrum signal bythe plurality of chip-sequence signals, with each chip-sequence signalfrom the plurality of chip-sequence signals having a different chipsequence from other chip-sequence signals in the plurality ofchip-sequence signals, respectively; a plurality of integrators coupledto said plurality of product devices, respectively, for integrating aplurality of products from the plurality of product devices during aperiod of a chip-sequence signal; a comparator, coupled to saidplurality of integrators, for selecting a largest value from theplurality of integrators; and a chip-sequence decoder, coupled to saidcomparator, for decoding the largest value from a respective integratorof said plurality of integrators, into N bits of interleaved data.
 4. Aspread-spectrum method improvement for sending data over acommunications channel, comprising the steps of: storing, at atransmitter, N bits of interleaved data as stored data, with N a numberof bits in a symbol; selecting, at said transmitter in response to the Nbits of stored data, a chip-sequence signal from a plurality of 2^(N)chip-sequence signals, as an output chip-sequence signal; transmitting,at said transmitter, the output chip-sequence signal as a radio wave, ata carrier frequency, over said communications channel, as aspread-spectrum signal; translating, at a receiver, the spread-spectrumsignal to a processing frequency as a received spread-spectrum signal;multiplying, at the processing frequency, for acquisition, the receivedspread-spectrum signal by a header chip-sequence signal from theplurality of chip-sequence signals, with each chip-sequence signal ofthe plurality of 2^(N) chip-sequence signals set for having an identicalchip sequence as the header chip-sequence signal, each chip-sequencesignal having a delay of at most one chip, with each chip-sequencesignal from the plurality of chip-sequence signals having a differentdelay from other chip-sequence signals; multiplying, after acquisition,the received spread-spectrum signal by the plurality of chip-sequencesignals, with each chip-sequence signal from the plurality ofchip-sequence signals having a different chip sequence from otherchip-sequence signals in the plurality of chip-sequence signals,respectively; integrating a plurality of products from the plurality ofproduct devices during a period of a chip-sequence signal; selecting alargest value from the plurality of integrators; and decoding thelargest value from a respective integrator of said plurality ofintegrators into N bits of interleaved data.